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| The 1Gb Double-Data-Rate-2 (DDR2) DRAMs is a highspeed CMOS Double Data Rate 2 SDRAM containing 1,073,741,824 bits. It is internally configured as an octal-bank DRAM. The 1Gb chip is organized as either 32Mbit x 4 I/O x 8 bank,16Mbit x 8 I/O x 8 bank or 8Mbit x 16 I/O x 8 bank device.These synchronous devices achieve high speed double-datarate transfer rates of up to 800 Mb/sec/pin for general applications.The chip is designed to comply with all key DDR2 DRAM key features: (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) normal and weak strength dataoutput driver, (4) variable data-output impedance adjustment and (5) an ODT (On-Die Termination) function. All of the control and address inputs are synchronized with apair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. A 14 bit address bus for x4 and x8 organised components and a 13 bit address bus for x16 component is used to convey row, column, and bank address devices. These devices operate with a single 1.8V +/- 0.1V power supply and are available in BGA packages. |
